CROSS-REFERENCE TO RELATED APPLICATION
This application is related to a co-pending patent application titled "DMOS Structure with Less Susceptibility to Latch-Up", by M. A. Shibib, Ser. No. 08/061,136, filed simultaneously with, and assigned to the same assignee, as this application.
1. Field of the Invention
This invention relates to metal-oxide-semiconductor devices in general and, more particularly, to a method of making doubly-diffused metal-oxide-semiconductor devices.
2. Description of the Prior Art
Conventional doubly-diffused metal-oxide-semiconductor (DMOS) devices may suffer from a parasitic bipolar transistor that can break down and destroy the DMOS device. Typically, the parasitic bipolar transistor has a lower breakdown voltage, when made conductive, than the DMOS device can withstand with the parasitic bipolar transistor turned off.
For example in FIG. 1, a simplified cross-section of a portion of N-channel DMOS transistor is shown. The DMOS transistor is shown having a source, a drain and a gate, the channel for the transistor being formed between the N+ type region and the N type drain when the surface of the P type layer is inverted by a suitable voltage on the gate. The parasitic NPN bipolar transistor is shown schematically having an emitter and collector in common with the source and drain of the DMOS transistor, respectively. The base of the bipolar transistor is formed by the P layer. When excess carriers in the bulk (N type drain region) of the device are swept into the junction of the N+ and P type layers (the emitter-base region of the parasitic bipolar transistor), the parasitic bipolar transistor can be forward biased. This typically happens when the drain voltage of the DMOS device is too rapidly changed. For example, when switching highly inductive loads, the drain voltage can change at several hundred volts per microsecond, causing the parasitic bipolar transistor to conduct and, if precautions are not taken, may destroy the DMOS transistor. This may also happen if carriers are generated by an avalanche breakdown of the N-type drain/P-type layer junction.
The above may also apply generally to other MOS controlled transistors, such as insulated gate bipolar transistors (IGBTs).
Thus, it is desirable to provide a DMOS (or IGBT) device that has less susceptibility to damage from fast drain (collector) voltage transients and avalanche breakdown.
Further, it is desirable to provide a DMOS (or IGBT) device with a higher avalanche energy tolerance for a given drain (collector) breakdown voltage or transient current.